A number of methods can be used for a current limiting circuit in which a power MOS (metal-oxide-semiconductor) transistor is used as an output transistor. In one method, a Zener diode is connected to a gate-source voltage to control a current of an output transistor by limiting the gate-source voltage to the Zener voltage. In another method, several diodes are connected to a gate-source voltage to control a current of an output transistor using the cumulative forward voltages of the diodes as a clamp. In yet another method, such voltage control is carried out using a voltage clamping circuit, or the like.
Referring to FIG. 5, a circuit schematic diagram of an output circuit including a conventional current limiting circuit is set forth and given the general reference character 500. In FIG. 5, a conventional current limiting circuit includes a voltage detecting circuit 501 and a current limiting portion 502.
Voltage detecting circuit 501 includes MOS transistors (M52, M53, and M54) and resistors (R55, R56, R58, and R59). Voltage detecting circuit 501 monitors an output terminal voltage Vout appearing at an output terminal of an output MOS transistor M1. Voltage detecting circuit 501 can be viewed as an overcurrent detecting portion. Current limiting portion 502 includes diodes (D51, D52, and D53). When voltage detecting circuit 501 judges that an overcurrent is being caused to flow through output transistor M1, current limiting portion 502 clamps the gate potential of output transistor M1 to a cumulative forward bias voltage across diodes (D51 to D53) to limit the current flowing through output transistor M1.
The operation of conventional current limiting circuit of output circuit 500 will now be explained with reference to the I-V load curve of FIG. 6 in conjunction with FIG. 5. In FIG. 6, it is assumed that a load LOAD illustrated in FIG. 5 is an incandescent lamp and an input voltage Vin is applied as a flash control signal for the incandescent lamp to an input terminal IN. When input voltage Vin is at a low level (e.g., at 0 volt), MOS transistor M1 is turned off. With MOS transistor M1 turned off, no current flows through MOS transistor M1 and output terminal voltage Vout becomes Vcc (e.g., 10 volts) as can be seen with load curve LOAD CURVE 1 which illustrates the I-V characteristics of the load LOAD.
Next, when signal Vin makes a transition to a high level (e.g., 5 volts), MOS transistor M1 starts to conduct current. The gate of MOS transistor M52 receives a voltage obtained by dividing the output terminal voltage Vout by a voltage divider circuit consisting of resistors (R55 and R56). If the output terminal voltage Vout is assumed to be VM under these conditions (see FIG. 6), when a relationship of R55/(R55+R56)·VM≧Vt52 is established, MOS transistor M52 is turned on (Vt52 is a threshold voltage of MOS transistor M52). That is, when Vout≧VM, MOS transistor M52 is turned on. VM can be expressed as (1+R56/R55)·Vt52. When MOS transistor M52 is turned on, the gate of MOS transistor M53 is pulled low and MOS transistor M53 is turned off. With MOS transistor M53 turned off, the gate of MOS transistor M54 becomes input voltage Vin, in this case a high level. Thus, MOS transistor M54 is turned on and a current flows from input terminal IN through a resistor R510, diodes (D1 to D3), and MOS transistor M54. In this way, the gate of MOS transistor M1 is clamped to the cumulative forward bias voltages of diodes (D1 to D3). Assuming the cumulative forward bias voltages of diodes (D1 to D3) is a constant Vs, then a gate to source voltage (Vgs) of MOS transistor M1 is fixed to Vs when Vout≧VM and a limited current value (Ilim1) flows through transistor M1.
In this state, a resistance Ra of the load LOAD is much larger than an internal resistance Rm1 of MOS transistor M1. Then, at the time when output terminal voltage Vout to be divided (note, the output terminal voltage Vout depends upon the resistances (Ra and Rm1, respectively) of load LOAD and MOS transistor M1) has become lower than VM, MOS transistor M52 is turned off. As a result, MOS transistor M53 is turned on and the gate of MOS transistor M54 is pulled low and MOS transistor M54 is turned off. Consequently, the current path from the gate of MOS transistor M1 through diodes (D1 to D3) is disabled and the gate of NMOS transistor M1 receives the full input voltage Vin applied to input terminal IN. In this way, the internal resistance Rm1 of MOS transistor M1 is further reduced and the output terminal voltage Vout settles to a normal operating point A(Va, Ia) as illustrated in FIG. 6. The normal operating point A(Va, Ia) depends on the resistance Ra of the load LOAD and the resistance Rm1 of MOS transistor M1.
Thus, at a time when a short-circuit failure, or the like, has occurred in a load LOAD, the output terminal voltage Vout is increased up to Vcc. However, when the output terminal voltage Vout reaches the above-mentioned voltage VM, MOS transistor M52 is turned on and thereby MOS transistor M54 is turned on to operate current limiting portion 502 and clamp the gate voltage of MOS transistor M1 and limit an output current. In this way, even if the load LOAD is short-circuited, an overcurrent is prevented from flowing through MOS transistor M1 and breakdown is prevented. Of course, the current limitation value ILIM1 is set so that even when a voltage Vcc is applied to the drain of MOS transistor M1, the source-drain current of MOS transistor M1 falls within a safe operating region.
However, in an output circuit 500 including a conventional current limiting circuit as described above, a problem arises in that when the resistance of the load LOAD is made smaller than Ra, the conventional current limiting circuit does not operate. For example, when the resistance of the load LOAD is a resistance Rb (in this case Rb is ½ Ra), the LOAD LOAD has an I-V characteristic as shown in load curve LOAD CURVE 2 in FIG. 6. Because the load LOAD is halved, the load current (Ib) becomes generally twice as large as Ia. Under this condition, the operating point is illustrated at point B(Vb, Ib). Here it is assumed that even in operating point B(Vb, Ib), the operation of MOS transistor M1 is sufficiently within the safe operating region. In this case, as long as the output circuit 500 is in the normal operating state, resistance Rb should be sufficiently driven.
However, as viewed from the load curve LOAD CURVE2, there is another quiescent state of operation for conventional output circuit 500 at operating point C(Vc, Ilim1). Thus, when the output terminal voltage is intended to go from Vcc to Vb in response to a change in the input voltage Vin, the operating point of the conventional output circuit 500 can settle at point C(Vc, Ilim1) and not reach point B(Vb, Ib). As described above, although the output circuit 500 has the ability to drive the load LOAD having a resistance Rb, the conventional current limiting circuit can become an encumbrance in reaching the desired quiescent operating point.
Consequently, if conventional output circuit 500 is to be capable of correctly driving when a load LOAD has a resistance Rb, the current limitation value Ilim1 must be changed. However, this approach causes the current limiting circuit to be individually provided for every product and a dedicated design needs to be carried out in accordance with the particular load condition. Therefore, costs may be increased.
One approach to solving the above-mentioned problem is disclosed in Japanese Patent Application Laid-Open 2000-2726 A (JP 2000-2726 A). In JP 2000-2726 A, a conventional output circuit is shown in which a plurality of conventional current limiting circuits having different current limitation values is self-contained therein. Any one of these conventional current limiting circuit is adapted to be selected with a switch in accordance with the load condition.
However, in a conventional output circuit as disclosed in JP 2000-2726 A, a plurality of switches must be suitably changed over in accordance with the load used and control of the change over is specifically required. Also, after setting (changing over) the switches, the current limitation value is fixed. Therefore, if the load is then changed, the conventional output circuit of JP 2000-2726 A can have the same problems as discussed above for the conventional output circuit 500 of FIG. 5.
Another conventional output circuit is set forth in a circuit schematic diagram in FIG. 7 and given the general reference character 700.
Conventional output circuit 700 includes a voltage detecting circuit 701, a voltage clamping circuit 702, an output transistor M1, a load LOAD, and a resistor R710.
Resistor R710 is connected between an input terminal IN and a gate of output transistor M1. Output transistor M1 has a source connected to ground GND and a drain connected to a terminal of load LOAD. Load LOAD has another terminal connected to a power supply Vcc. Voltage detecting circuit 701 is connected to receive an input signal from input terminal IN and an output voltage Vout from the drain of output transistor M1 and enables the voltage clamping circuit 702. Voltage clamping circuit 702 is connected between the gate of output transistor M1 and ground GND.
Voltage detecting circuit 701 includes resistors (R75 to R79) and transistors (M72 to M74). Resistors (R75 and R76) are connected in series between the output voltage Vout and ground GND. Resistor R78 and transistor M72 are connected to form an inverter. Resistor R79 and transistor M73 are connected to form an inverter. The inverter (R78 and M72) has an input connected to receive a voltage provided at a tap point connection between resistors (R75 and R76) and an output connected to the inverter (R79 and M73). The inverter (R79 and M73) has an output connected to a gate of transistor M74. Transistor M74 has a source connected to ground GND and a drain connected to a drain of a transistor M75 of voltage clamping circuit 702.
Voltage clamping circuit 702 includes a transistor M75 and resistors (R71 and R72). Resistors (R71 and R72) are connected in series between the gate of output transistor M1 and ground GND. Transistor M75 has a gate connected to a tap point formed at the connection of resistors (R71 and R72) and a drain connected to the gate of output transistor M1.
Voltage detecting circuit 701 is enabled when an input signal at input terminal IN is at a high level. When enabled, voltage detecting circuit 701 detects a voltage level of output voltage Vout. If the output voltage Vout is greater than a predetermined output voltage, transistor M74 is turned on and voltage clamping circuit 702 is enabled to clamp the gate of output transistor M1 to a predetermined voltage. If the output voltage Vout is less than the predetermined output voltage, transistor M74 is turned off and voltage clamping circuit 702 is disabled.
In this way, conventional output circuit 700 provides a load curve characteristic as illustrated in FIG. 6 and having only a current limitation value Ilim1. Thereby, conventional output circuit 700 has the same drawbacks as conventional output circuit 500.
In light of the above, it would be desirable to provide an output circuit in which a value of a limited current flowing through an output transistor may be changed in a plurality of stages in response to a value of an output voltage of the output transistor. In particular, it would be desirable that a value of a limited current may be increased in response to a decrease in an output voltage.